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The GameBoy is based on the Zilog Z80 processor. There are seven main
registers (A, B, C, D, E, H, L) all are 8bit registers, six of these can pair together to
make three 16bit registers (BC, DE, HL). There is also a Flags (F) register, which
for the purposes of some commands is paired with the A register to make a 16bit register (AF)
, a Stack Pointer and a Program Counter. Following is a table showing these as well as
the bits of the flags register.
REGISTERS
| HIGH BYTE (bits 15 - 8 if paired) |
LOW BYTE (bits 7 - 0) |
DESCRIPTION |
| A |
F |
Accumulator / Flags registers |
| B |
C |
General Purpose Registers |
| D |
E |
General Purpose Registers |
| H |
L |
General Purpose Registers - Usually a memory pointer |
| SP |
Stack Pointer |
| PC |
Program Counter |
FLAGS REGISTER
| BIT NUMBER |
FLAG |
DESCRIPTION |
| 7 |
Z |
Zero Flag. Set if the last math operation resulted in a zero |
| 6 |
N |
Subtract Flag. Set if the last math operation involved a subtraction |
| 5 |
H |
Half Carry Flag. Set if the last math operation cause a carry from the lower nibble (bit 3-4) |
| 4 |
C |
Carry Flag. Set if the last math operation cause a carry (bit 7-8) |
| 3 |
X |
Not Used |
| 2 |
X |
Not Used |
| 1 |
X |
Not Used |
| 0 |
X |
Not Used |
COMMAND DESCRIPTIONS
ADC x, y
ADD x, y
AND x
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Add y + CF to x
Add y to x
And x to A
|
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BIT b, x
|
Test bit b of x
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CALL c, x
CALL x
CCF
CP x
CPL
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If condition c is true, call subroutine x
Call subroutine x
Complement carry flag
Compare A with x
Complement A
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DAA
DEC x
DI
|
Decimal adjust A
Decrement x by 1
Disable interrupts
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|
EI
|
Enable interrupts
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|
HALT
|
Halt (wait for interrupt or reset)
|
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INC x
|
Increment x by 1
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JP c, x
JP x
JR c, d
JR d
|
If condition c is true jump to location x
Jump to location x
If condition c is true jump relative by d
Jump relative by d
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LD x, y
LDD x, y
LDI x, y
|
Load x with y
Load A with (HL), DEC HL
Load A with (HL), INC HL |
|
NOP
|
No operation
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|
OP x
|
OR x to A
|
POP x
PUSH x
|
Pop x from the top of the stack, updating SP
Push x onto the top of the stack, updating SP
|
RES b, x
RET
RET c
RETI
RST x
|
Reset bit b of x
Return from subroutine
If condition c is true, return from subroutine
Return from interrupt
Call subbroutine at x (x = 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h)
|
SBC x
SCF
SET b, x
STOP
SUB x
SWAP x
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Subtract y + CF from x
Set carry flag
Set bit b of x
Stop CPU until P1-P10 go high
Subtract x from A
Swap register nibbles
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XOR x
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XOR x to A
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COMMANDS
Please note that the timings for the instructions are given in Machine Cycles, to convert
these to Clock Cycles just multiply the number by four. The four columns Z,N,H,C
refer to the flags in the flags register, 0 means reset, 1 means set, X means set
as expected (i.e. if the result is zero then the zero flags would be set, else reset) and
blank means it is not effected.
| |
Op-code |
Destination |
Source |
Z |
N |
H |
C |
M/C |
Bytes |
A |
ADC A, (HL)
ADC A, n8
ADC A, r8
|
A
A
A
|
(HL)
8bit integer
A, B, C, D, E, H, L
|
X
X
X
|
0
0
0
|
X
X
X
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X
X
X
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2
2
1
|
1
2
1
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ADD A,(HL)
ADD A, n8
ADD A, r8
ADD HL, r16
ADD SP, e8
|
A
A
A
HL
SP
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(HL)
8bit integer
A, B, C, D, E, H, L
BC, DE, SP
8bit offset
|
X
X
X
0
|
0
0
0
0
0
|
X
X
X
X
X
|
X
X
X
X
X
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2
2
1
2
4
|
1
2
1
1
2
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AND (HL)
AND n8
AND r8
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A
A
A
|
(HL)
8bit integer
A, B, C, D, E, H, L
|
X
X
X
|
0
0
0
|
1
1
1
|
0
0
0
|
2
2
1
|
1
2
1
|
B |
BIT n3, (HL)
BIT n3, r8
|
Zero Flag
Zero Flag
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(HL)
A, B, C, D, E, H, L
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X
X
|
0
0
|
1
1
|
|
3
2
|
2
2
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| C |
CALL cc, n16
CALL n16
|
PC
PC
|
16bit address
16bit address
|
|
|
|
|
6/3
6
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3
3
|
|
CCF
|
Carry Flag
|
|
|
0
|
0
|
X
|
1
|
1
|
CP (HL)
CP n8
CP r8
|
Flags
Flags
Flags
|
(HL)
8bit integer
A, B, C, D, E, H, L
|
X
X
X
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1
1
1
|
X
X
X
|
X
X
X
|
2
2
1
|
1
2
1
|
|
CPL
|
A
|
A
|
|
1
|
1
|
|
1
|
1
|
| D |
DAA
|
A
|
A
|
X
|
|
0
|
X
|
1
|
1
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DEC (HL)
DEC r16
DEC r8
|
(HL)
BC, DE, HL, SP
A, B, C, D, E, H, L
|
(HL)
BC, DE, HL, SP
A, B, C, D, E, H, L
|
X
X
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1
1
|
X
X
|
|
3
2
1
|
1
1
1
|
|
DI
|
|
|
|
|
|
|
1
|
1
|
| E |
EI
|
|
|
|
|
|
|
1
|
1
|
| H |
HALT
|
|
|
|
|
|
|
1
|
1
|
| I |
INC (HL)
INC r16
INC r8
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(HL)
BC, DE, HL, SP
A, B, C, D, E, H, L
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(HL)
BC, DE, HL, SP
A, B, C, D, E, H, L
|
X
X
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0
0
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X
X
|
|
3
2
1
|
1
1
1
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| J |
JP (HL)
JP cc, n16
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PC
PC
|
(HL)
16bit address
|
|
|
|
|
1
4/3
|
1
3
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JP n16
JR cc, e8
JR e8
|
PC
PC
PC
|
16bit address
8bit offset
8bit offset
|
|
|
|
|
4
3/2
3
|
3
2
2
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| L |
LD (C), A
LD (HL), n8
LD (HL), r8
LD (n16), A
LD (n16), SP
LD (r16), A
LD A, (C)
LD A, (n16)
LD A, (r16)
LD HL, SP + e8
LD r16, n16
LD r8, (HL)
LD r8, n8
LD r8, r8
LD SP, HL
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(C)
(HL)
(HL)
(16bit address)
(16bit address)
(BC), (DE), (HL)
A
A
A
HL
BC, DE, HL, SP
A, B, C, D, E, H, L
A, B, C, D, E, H, L
A, B, C, D, E, H, L
SP
|
A
8bit integer
A, B, C, D, E, H, L
A
SP
A
(C)
(16bit address)
(BC), (DE), (HL)
SP + 8bit offset
16bit integer
(HL)
8bit integer
A, B, C, D, E, H, L
HL
|
0
|
0
|
X
|
X
|
2
3
2
4
5
2
2
4
2
3
3
2
2
1
2
|
1
2
1
3
3
1
1
3
1
2
3
1
2
1
1
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LDD (HL), A
LDD A, (HL)
|
(HL)
A
|
A
(HL)
|
|
|
|
|
2
2
|
1
1
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LDH (e8), A
LDH A, (e8)
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(8bit offset)
A
|
A
(8bit offset)
|
|
|
|
|
3
3
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2
2
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LDI (HL), A
LDI A, (HL)
|
(HL)
A
|
A
(HL)
|
|
|
|
|
2
2
|
1
1
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| N |
NOP
|
|
|
|
|
|
|
1
|
1
|
| O |
OR (HL)
OR n8
OR r8
|
A
A
A
|
(HL)
8bit integer
A, B, C, D, E, H, L
|
X
X
X
|
0
0
0
|
0
0
0
|
0
0
0
|
2
2
1
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1
2
1
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| P |
POP r16
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AF, BC, DE, HL
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(SP)
|
|
|
|
|
3
|
1
|
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PUSH r16
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(SP)
|
AF, BC, DE, HL
|
|
|
|
|
4
|
1
|
| R |
RES n3, (HL)
RES n3, r8
|
Bit in memory
Bit in register
|
(HL)
A, B, C, D, E, H, L
|
|
|
|
|
3
2
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2
2
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RET
RET cc
|
PC
PC
|
Condition Flag
|
|
|
|
|
4
5/2
|
1
1
|
|
RETI
|
PC
|
|
|
|
|
|
4
|
1
|
RL (HL)
RL r8
|
(HL)
A, B, C, D, E, H, L
|
(HL)
A, B, C, D, E, H, L
|
X
X
|
0
0
|
0
0
|
X
X
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4
2
|
2
2
|
|
RLA
|
A
|
A
|
0
|
0
|
0
|
X
|
1
|
1
|
RLC (HL)
RLC r8
|
(HL)
A, B, C, D, E, H, L
|
(HL)
A, B, C, D, E, H, L
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X
X
|
0
0
|
0
0
|
X
X
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4
2
|
2
2
|
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RLCA
|
A
|
A
|
0
|
0
|
0
|
X
|
1
|
1
|
RR (HL)
RR r8
|
(HL)
A, B, C, D, E, H, L
|
(HL)
A, B, C, D, E, H, L
|
X
X
|
0
0
|
0
0
|
X
X
|
4
2
|
2
2
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RRA
|
A
|
A
|
0
|
0
|
0
|
X
|
1
|
1
|
RRC (HL)
RRC r8 |
(HL)
A, B, C, D, E, H, L |
(HL)
A, B, C, D, E, H, L |
X
X |
0
0 |
0
0 |
X
X |
4
2 |
2
2 |
| RRCA |
A |
A |
0 |
0 |
0 |
X |
1 |
1 |
| RST f |
PC |
|
|
|
|
|
4 |
1 |
| S |
SBC A, (HL)
SBC A, n8
SBC A, r8 |
A
A
A |
(HL)
8bit integer
A, B, C, D, E, H, L |
X
X
X |
1
1
1 |
X
X
X |
X
X
X |
2
2
1 |
1
2
1 |
| SCF |
Carry Flag |
|
|
0 |
0 |
1 |
1 |
1 |
SET n3, (HL)
SET n3, r8 |
Bit in memory
Bit in memory |
(HL)
A, B, C, D, E, H, L |
|
|
|
|
3
2 |
2
2 |
SLA (HL)
SLA r8 |
(HL)
A, B, C, D, E, H, L |
(HL)
A, B, C, D, E, H, L |
X
X |
0
0 |
0
0 |
X
X |
4
2 |
2
2 |
SRA (HL)
SRA r8 |
(HL)
A, B, C, D, E, H, L |
(HL)
A, B, C, D, E, H, L |
X
X |
0
0 |
0
0 |
X
X |
4
2 |
2
2 |
SRL (HL)
SRL r8 |
(HL)
A, B, C, D, E, H, L |
(HL)
A, B, C, D, E, H, L |
X
X |
0
0 |
0
0 |
X
X |
4
2 |
2
2 |
| STOP |
|
|
|
|
|
|
1 |
2 |
SUB (HL)
SUB n8
SUB r8 |
A
A
A |
(HL)
8bit integer
A, B, C, D, E, H, L |
X
X
X |
1
1
1 |
X
X
X |
X
X
X |
2
2
1 |
1
2
1 |
SWAP (HL)
SWAP r8 |
(HL)
A, B, C, D, E, H, L |
(HL)
A, B, C, D, E, H, L |
X
X |
0
0 |
0
0 |
0
0 |
4
2 |
2
2 |
| X |
XOR (HL)
XOR n8
XOR r8 |
A
A
A |
(HL)
8bit integer
A, B, C, D, E, H, L |
X
X
X |
0
0
0 |
0
0
0 |
0
0
0 |
2
2
1 |
1
2
1 |
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